Ultrashort vertical-channel MoS2 transistor using a self-aligned contact

Fabrication processes of self-aligned vertical transistor

Figure 1a–f schematically illustrates the fabrication processes of our self-aligned vertical device, and the corresponding optical images are also included in Supplementary Fig. 1. To fabricate the device, a graphene/BN/MoS₂ vdW heterostructure is first stacked using dry alignment transfer process under optical microscope, as shown in Fig. 1a and detailed in the Method section. Within this three-layer structure, the top graphene works as the gate electrode, middle BN layer (5 to 20 nm thick) works as gate dielectric, and…