The understanding of the impact of efficiently optimized underlap length on analog/RF performance parameters of GNR-FETs

To begin the analysis, the current simulator is calibrated to correspond to the device structure presented in Ref.³⁹. Figure 2 demonstrates that obtained simulations are in good agreement with previous research findings.

Once the correctness of the simulation with the above-described methodology has been established, an underlap is introduced in the body of the GNR-FET at the drain end to assess the impact of Asymmetric underlap (UL) length on the performance of GNR-FET devices. It is important to clarify…